In integrated circuit (IC) devices, resistive random access memory (RRAM) is an emerging technology for next generation non-volatile memory devices. A RRAM structure includes an array of RRAM cells each of which stores a bit of data using resistance values, rather than electronic charge. Particularly, each RRAM cell includes a resistive material layer, the resistance of which can be controlled to be high or low to represent logic “0” or logic “1”, respectively. High and low and resistances each should have a large and stable resistance window for reliable readings.
In advanced technology nodes, the feature size scales down and the size of memory devices is reduced accordingly. However, the reduction of the RRAM devices causes poor endurance issue. During applications of a RRAM cell, the RRAM cell experiences a greater number of set and reset operation cycles. The initial resistance window is degraded after long time cycling, introducing reliability issue. It is important to have a small size RRAM cells with stable resistance window and good enduring performance.
Accordingly, it would be desirable to provide an improved RRAM structure and a method of manufacturing thereof absent the disadvantages discussed above.